System fault-tolerance analysis of COTS-based satellite on-board computers

• Published in: Microelectronics 2014-10, Vol.45 (10), p.1335-1341
• Main Authors: Burlyaev, Dmitry, van Leuken, Rene
• Format: Article
• Language: English
• Subjects: Fault-tolerance techniques; FMEA; Satellite dependability; System-on-chip; SystemC modeling
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2014.01.007

Fault-tolerance analysis reveals possible system behavior under the influence of faults. Such analysis is essential for satellites where faults might be caused by space radiation and autonomous recovery is needed. In this paper we present a statistical simulation approach for fault-tolerance analysis of satellite On-Board Computers (OBCs) that are based on Commercial Off-The-Shelf (COTS) components. Since the logic level of COTS electronics is unknown to satellite designers, a new higher-level fault-tolerance analysis is required. We propose such technique that relies on OBC modeling and fault modeling, based on the modeling principle of Single-Event Upsets (SEUs). For the first time we can compare the efficiency of fault-tolerance techniques implemented in software and Field-Programmable Gate Array (FPGA). In addition, our approach enables to analyze system fault-tolerance at early development stages. In a case study the approach is applied to an OBC with a Microsemi SmartFusion SoC, that executes a satellite attitude control algorithm. The gained statistical simulation results enabled 50% reduction in the hardware overhead of the implemented memory scrubbing technique without loss in fault-tolerance. Our method revealed critical fault-tolerance drawbacks of the initial system design that could have lead to satellite mission failure.