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Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in...

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Bibliographic Details
Published in:Microelectronics 2024-08, Vol.150, p.106261, Article 106261
Main Authors: Kong, Moufu, Deng, Hongfei, Luo, Yingzhi, Zhu, Jiayan, Yi, Bo, Yang, Hongqiang, Hu, Qiang, Meng, Fanxin
Format: Article
Language:English
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Summary:In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device. •The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of the N-drift region, but also optimizes the electric field distribution in the drift region.•The left side of the P-top region is connected to the source, which suppresses the channel length modulation effect of the proposed LDMOS, thereby diminishing the saturation current and enhancing the short-circuit capacity of the device.•Simulation results indicate that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.
ISSN:1879-2391
1879-2391
DOI:10.1016/j.mejo.2024.106261