Soft errors in DNN accelerators: A comprehensive review

• Published in: Microelectronics and reliability 2020-12, Vol.115, p.113969, Article 113969
• Main Authors: Ibrahim, Younis, Wang, Haibin, Liu, Junyang, Wei, Jinghe, Chen, Li, Rech, Paolo, Adam, Khalid, Guo, Gang
• Format: Article
• Language: English
• Subjects: ASIC; Deep learning; DNN accelerators; FPGA; GPU; Reliability; Soft errors
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2020.113969

Deep learning tasks cover a broad range of domains and an even more extensive range of applications, from entertainment to extremely safety-critical fields. Thus, Deep Neural Network (DNN) algorithms are implemented on different systems, from small embedded devices to data centers. DNN accelerators have proven to be a key to efficiency, as they are even more efficient than CPUs. Therefore, they have become the major executing hardware for DNN algorithms. However, these accelerators are susceptible to several types of faults. Soft errors pose a particular threat because the high-level parallelism in these accelerators can propagate a single failure to multiple errors in the next levels until the model predictions' output is affected. This article presents a comprehensive review of the reliability of the DNN accelerators. The study begins by reviewing the widely assumed claim that DNNs are inherently tolerant to faults. Then, the available DNN accelerators are systematically classified into several categories. Each is individually analyzed; and the commonly used accelerators are compared in an attempt to answer the question, which accelerator is more reliable against transient faults? The concluding part of this review highlights the gray areas of the DNNs and predicts future research directions that will enhance its applicability. This study is expected to benefit researchers in the areas of deep learning, DNN accelerators, and reliability of this efficient paradigm.