SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability

• Published in: Microelectronics and reliability 2024-06, Vol.157, p.115418, Article 115418
• Main Authors: Chen, De-Xin, Wang, Ying, Song, Yan-Xing, Fei, Xin-Xing, Huang, Hao
• Format: Article
• Language: English
• Subjects: Avalanche robust; Silicon carbide (SiC); Super-junction MOSFET (SJ-MOSFET); Unclamped inductive switch (UIS)
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2024.115418

In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10−3 s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 1017 cm−3 under the same avalanche duration range. •The UIS burnout mechanism of SIC super-junction MOSFET is mainly due to the uneven current and temperature distribution caused by parasitic transistor conduction, which leads to device burnout.•The UIS performance of the proposed silicon carbide layered super-junction MOSFET has been significantly improved.•The improved performance of UIS is mainly due to the hierarchical non-uniform structure which restrains parasitic transistor conduction without sacrificing breakdown voltage.