FPGA-based interrogation controller with optimized pipeline architecture for very large-scale fiber-optic interferometric sensor arrays

• Published in: Optics and lasers in engineering 2019-10, Vol.121, p.389-396
• Main Authors: Cui, Ke, Peng, Wenjun, Ren, Zhongjie, Qian, Jieyu, Zhu, Rihong
• Format: Article
• Language: English
• Subjects: Field programmable gate array (FPGA); Interferometric sensor; Interrogation controller; Multiplexing; Time division multiplexing (TDM)
• ISSN: 0143-8166; 1873-0302
• DOI: 10.1016/j.optlaseng.2019.04.026

•Detailed FPGA resource budget analysis is provided to certify that latency is the most important factor to support large scale sensor array.•This paper presents a complete design of the interrogation controller based on FPGA with optimized pipeline to reduce latency.•To the best of our knowledge, it is the first work to build the real-time interrogation controller that can support more than 1000 sensors. Fiber-optic sensor arrays are always organized utilizing hybrid time division multiplexing (TDM)/wavelength division multiplexing (WDM) techniques to share some common optical components and reduce the cost. Modern sensor arrays can support up to several thousands of sensors by employing distributed amplification technique. They generate huge amount of data and pose other big challenge on the interrogation controller of the sensor system, such as long demodulation time and heavy computational burden. Aiming to solve these problems, we present a complete design of the interrogation controller based on a field programmable gate array (FPGA) by lending its powerful parallelism potential. The interrogation controller adopts a hardware-implementation-friendly modulation method called the rectangular-pulse binary (RPB) modulation. The functional modules in the FPGA are properly organized according to the working principle of the RPB method and carefully designed by optimizing their pipeline architecture to minimize the output latency, which is essential to increase the maximal supportable number of sensors. By analyzing the resource budget and the actual resource consumption result, it demonstrates that the controller can support up to 1000+ sensors in real time by using a single middle-end Stratix III FPGA chip. A 8-sensors array prototype is constructed to validate its functionality. This work can greatly reduce the cost of the sensor system and push it closer to the practical applications.