Timing verification of rapid single flux quantum logic cell

• Published in: Physica. C, Superconductivity Superconductivity, 2023-07, Vol.610, p.1354285, Article 1354285
• Main Authors: Weng, Bicong, Gao, Xiaoping, Ren, Jie, Li, Xiuting, Niu, Minghui, Yang, Shucheng, Wang, Zhen
• Format: Article
• Language: English
• Subjects: Hold time test; Process corner; Setup time test; Single-flux quantum logic; Superconducting electronics; Timing verification
• ISSN: 0921-4534; 1873-2143
• DOI: 10.1016/j.physc.2023.1354285

•Digital simulation is efficient and resource-effective for RSFQ LSI circuit design, but its reliability depends on timing parameters extracted from analog simulation.•A closed-loop verification process for timing parameters, including delay, setup time, and hold time, is essential.•Current verification methods can only measure delay, but a new method introduced in this paper can estimate both setup time and hold time in addition to delay.•The proposed timing verification method is efficient and reliable, as confirmed by a closed-loop verification process between simulation and measurement.•The measured timing parameters can improve the reliability of static timing analysis in circuit design and increase the yield of circuits after fabrication. Digital simulation is popular in rapid single flux quantum (RSFQ) large-scale integrated (LSI) circuit design for its high efficiency and low resource requirements. However, its reliability highly depends on the timing parameters extracted by analog simulation. Therefore, it is essential to establish a closed-loop verification process of the timing parameters, including delay, setup time (ST), and hold time (HT). Current verification methods, which utilize the ring oscillator, can only measure the delay of the SFQ cells and any circuit structure that can efficiently test ST and HT have yet to be reported. In this paper, we will introduce a timing verification method that can finely estimate the delay, ST, and HT of RSFQ sequential cells. The resolution of our unique test circuit is one Josephson junction delay in the Josephson transmission line (JTL). We also perform a closed-loop verification process between simulation and measurement by bringing the process parameters derived from the process control monitor (PCM) on the same batch back to the post-simulation. The process parameters contain Josephson junction critical current density JC and the sheet resistance of the Mo resistor RSh. With our method, the post-simulation analysis of several cells' delay, ST, and HT in the SIMIT-Nb03 cell library closely follows the test results. The consistency between the simulation and test indicates that the proposed timing verification method is efficient and reliable. With the measured timing parameters of cells, the reliability of the static timing analysis (STA) in circuit design before tape-out would be increased, which would improve the yield of circuits after fabrication.