FSM Based VLSI Architecture for Decision Based Neighborhood Referred Asymmetrical Trimmed Variant Filter

• Published in: Procedia computer science 2019, Vol.152, p.130-139
• Main Authors: Vasanth, K., Shireesha, N., Sivakumar, V.G., Vadivel, M., Ravi, C.N., soumya, Lalitha, Ganesan, P.
• Format: Article
• Language: English
• Subjects: Asymmetrical Trimmed variants filter; Finite State Machine; One Hot Encoding; Salt and Pepper noise
• ISSN: 1877-0509; 1877-0509
• DOI: 10.1016/j.procs.2019.05.035

A VLSI architecture using Finite State Machine Based for logic based vicinity inferred asymmetrically trimmed variants filter is proposed. The filter was checked on MATLAB environment and found to suppress high density salt and pepper noise. For better speed & power constraints the algorithm was implemented on VIRTEX FPGA using VHDL as part of system on chip implementation. The Proposed VLSI architecture uses one hot encoding for Finite state machine implementation of the filter. The architecture has 5 different modules and each computes the desired values using Finite state machine. There are three main computations implemented in this filter as separate module titled asymmetrical trimmed median, Midpoint, Mean of 4 Neighbors and local mean. The FSM uses one hot encoding Technique for lower power consumption. The architecture was targeted on FPGA device XCV1000-4bq560 using VHDL. The synthesis of the architecture utilizes 2744 slices of FPGA, operates at 54.630 MHz frequency and consumes 32 mw of power.