An inner gate as enabler for vertical pitch scaling in macaroni channel gate-all-around 3-D NAND flash memory

Scaling the vertical cell pitch to increase bit density in 3-D NAND flash memories degrades both the cell transistor characteristics and the memory operation. Here, we therefore investigate an inner gate to mitigate the scaling impact in macaroni channel devices. We evaluate several scenarios with v...

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Bibliographic Details
Published in:Solid-state electronics 2023-01, Vol.199, p.108498, Article 108498
Main Authors: Verreck, D., Arreghini, A., den bosch, G. Van, Rosmeulen, M.
Format: Article
Language:English
Subjects:
CMOS-based memories
DRAM
Flash
Memory devices
SRAM
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Summary:Scaling the vertical cell pitch to increase bit density in 3-D NAND flash memories degrades both the cell transistor characteristics and the memory operation. Here, we therefore investigate an inner gate to mitigate the scaling impact in macaroni channel devices. We evaluate several scenarios with varying complexity using calibrated TCAD simulations: from keeping the inner gate voltage grounded to coupling it to the read gate. We find a trade-off between improved cell transfer characteristics and program voltage determined by the inner gate to read gate coupling ratio. •Scaling vertical pitch in 3-D NAND flash memory degrades cell performance.•An inner gate can mitigate the scaling-induced degradation.•A trade-off exists between cell characteristics (Vth, Ion) and program voltage.•The trade-off depends on the inner gate to read gate voltage coupling ratio.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2022.108498