Recessed-Channel WSe 2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

• Published in: ACS nano 2022-05, Vol.16 (5), p.8484-8492
• Main Authors: Lee, Dongryul, Choi, Yongha, Kim, Junghun, Kim, Jihyun
• Format: Article
• Language: English
• ISSN: 1936-0851; 1936-086X
• DOI: 10.1021/acsnano.2c03402

Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III-V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe ) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe FET are systematically monitored during this layer-by-layer recess-channel process. The WSe etching rate is estimated to be 2-3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WO ) layer grown through ultraviolet-ozone treatment induces robust p-doping in the neighboring (or underlying) WSe through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe FETs enables the realization of a high on/off output current ratio (>10 ) and field-effect mobility (∼190 cm /V·s), while maintaining low contact resistance (0.9-6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.