One dimensional MOSFETs for sub-5 nm high-performance applications: a case of Sb 2 Se 3 nanowires

Low-dimensional materials have been proposed as alternatives to silicon-based field-effect transistor (FET) channel materials in order to overcome the scaling limitation. In the present research, gate-all-around (GAA) Sb Se nanowire FETs were simulated using the quantum transport method. The gate-le...

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Bibliographic Details
Published in:Physical chemistry chemical physics : PCCP 2023-01, Vol.25 (3), p.2056-2062
Main Authors: Tan, Xingyi, Li, Qiang, Ren, Dahua
Format: Article
Language:English
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Summary:Low-dimensional materials have been proposed as alternatives to silicon-based field-effect transistor (FET) channel materials in order to overcome the scaling limitation. In the present research, gate-all-around (GAA) Sb Se nanowire FETs were simulated using the quantum transport method. The gate-length ( , = 5 nm) GAA Sb Se FETs with an underlap (UL, UL = 2, 3 nm) could satisfy the on-state current ( ) and delay time ( ) of the 2028 requirements for high performance (HP) applications of the International Technology Roadmap for Semiconductors (ITRS) 2013. It is interesting that the = 3 nm GAA Sb Se FETs with a UL = 3 nm can meet the , power dissipation (PDP), and of the 2028 requirements of ITRS 2013 for HP applications. Therefore, GAA Sb Se FETs can be a potential candidate scaling Moore's law downward to 3 nm.
ISSN:1463-9076
1463-9084
DOI:10.1039/D2CP05132J