Modification and hardware implementation of cortex-like object recognition model

• Published in: IET image processing 2020-12, Vol.14 (14), p.3490-3498
• Main Authors: Mohammadi Anbaran, Alireza, Torkzadeh, Pooya, Ebrahimpour, Reza, Bagheri, Nasour
• Format: Article
• Language: English
• Subjects: application‐specific integrated circuit implementation; biologically motivated object recognition model; computational intensive nature; computational object recognition models; configurable hardware; cortex‐like object recognition model; field programmable gate arrays; field‐programmable gate array; FPGA; hardware implementation; hardware resource usage; hierarchical model; HMAX model; ISE; massive parallel processing; object recognition; position tolerance; Research Article; software implementation; Virtex 6 family; visual cortex; XC6VLX240T platform; Xilinx
• ISSN: 1751-9659; 1751-9667
• DOI: 10.1049/iet-ipr.2019.0264

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.