Fabrication process development for superconducting VLSI circuits: minimizing plasma charging damage

• Published in: Journal of physics. Conference series 2008-02, Vol.97 (1), p.012227
• Main Authors: Tolpygo, S K, Amparo, D
• Format: Article
• Language: English
• Subjects: Aluminum; Charging; Critical current (superconductivity); Damage assessment; Digital electronics; Electrical grounding; Electrical junctions; Ground plane; Integrated circuits; Josephson junctions; Niobium; Physics; Plasma; Plasma processing; Plasmas (physics); Superconductivity; Tunnel junctions; Very large scale integration
• ISSN: 1742-6596; 1742-6588; 1742-6596
• DOI: 10.1088/1742-6596/97/1/012227

In order to realize the potential of superconducting digital integrated circuits and make them competitive with semiconductor ICs, their integration scale must be increased from a current level of ~ 104 Josephson junctions (JJs) per chip to a VLSI level, and the maximum clock frequency, currently ~ 30 GHz, must also be increased above 50 GHz. It is shown that the main factor preventing successful fabrication of VLSI superconducting digital circuits is variations of the Josephson critical currents in logic cells caused by plasma-induced charging damage (electric stress) to the ultra thin oxide tunnel barrier of JJs. The results are presented for Nb/Al/AlOx/Nb tunnel junctions fabricated on 150-mm wafers by an 11-level process for superconducting integrated circuits. It is shown that, as a result of charging in processing plasmas, the critical current Ic of JJs becomes dependent on the way the junctions are connected to the circuit ground plane and interconnected with other circuit elements. For instance, the Ic of the grounded junctions may abnormally increase with respect to the Ic of the floating junctions. Depending on the processing plasma parameters, plasma charging can damage all junctions in a circuit or only some specific junctions, e.g., the smallest in size. In addition to the Ic enhancement, the damage also reveals itself as increased subgap conduction in tunnel junctions and as an enhanced spread of the critical currents of the same-size junctions, a result of the statistical nature of the oxide barrier breakdown under electric stress. The plasma damage model is proposed and the most damaging plasma processing fabrication steps are discussed as well as the ways of minimizing the plasma-induced charging damage to superconducting integrated circuits.