The single chip versus multichip packaging option for digital CMOS in the 1990s

• Published in: IEEE transactions on components, hybrids, and manufacturing technology hybrids, and manufacturing technology, 1992-10, Vol.15 (5), p.915-922
• Main Authors: Neugebauer, C.A., Fillion, R.A., Daum, W., Gdula, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Chip scale packaging; Clocks; CMOS logic circuits; CMOS technology; Costs; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Microprocessor chips; Multichip modules; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Senior members; Ultra large scale integration; Very large scale integration
• ISSN: 0148-6411; 1558-3082
• DOI: 10.1109/33.180058

The level of functional density achievable in digital CMOS logic chips is so high that in the past systems implementations by multichip module (MCM) packaging appear to have been unnecessary, because the system was usually made up of only a few chips. However, rapidly increasing system sizes anticipated in the future will require many VLSI/ULSI CMOS chips per system, operating at near 100 MHz clock frequency. The authors have, therefore, reexamined the single-chip versus MCM packaging option for digital CMOS for the 1990s. They conclude that, for large-scale CMOS logic systems constructed by the use of many state-of-the-art VLSI/ULSI chips, the MCM packaging approach gives a manyfold improvement in packing density (3-8*), performance (up to 1.4*), and cost (1.2*) over the SCM packaging approach.< >