Network subsystem design

It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation. This makes it essential that the number of times network data traverses the CPU/memory data path be minimized. Evidence wh...

Full description

Saved in:
Bibliographic Details
Published in:IEEE network 1993-07, Vol.7 (4), p.8-17
Main Authors: Druschel, P., Abbott, M.B., Pagels, M.A., Peterson, L.L.
Format: Article
Language:English
Subjects:
Application software
Bandwidth
Central Processing Unit
Computer science
FDDI
High-speed networks
Protection
Protocols
Throughput
Workstations
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation. This makes it essential that the number of times network data traverses the CPU/memory data path be minimized. Evidence which suggests that the cache cannot be expected to significantly reduce the number of data movements over this path is reviewed. Hardware and software techniques for avoiding the CPU/memory bottleneck are discussed. It is concluded that naively applying these techniques is not sufficient for achieving good application-to-application throughput; they must also be carefully integrated. Various techniques that can be integrated to provide a high bandwidth data path between I/O devices and application programs are outlined.< >
ISSN:0890-8044
1558-156X
DOI:10.1109/65.224051