Configurable Ring Oscillator PUF Using Hybrid Logic Gates

• Published in: IEEE access 2020-01, Vol.8, p.1-1
• Main Authors: Deng, Ding, Hou, Shen, Wang, Zhenyu, Guo, Yang
• Format: Article
• Language: English
• Subjects: Application specific integrated circuits; Circuit design; Configurable Ring Oscillator; Delays; Field programmable gate arrays; Gates (circuits); Hardware; Hardware security; Integrated circuits; Logic circuits; Logic gates; Multiplexing; Oscillators; Physical Unclonable Function; Random access memory; Ring oscillators
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2020.3021205

Physical unclonable function (PUF), a hardware that can extract the differences of the same implementations and provide unique secret keys without the utilization of non-volatile memory, is regarded as a promising security primitive in the near future. Ring Oscillator (RO) PUF is one of its easy silicon implementations, which exploits the frequency difference between a pair of structurally identical ring oscillators. However, a large number of ROs must be constructed if multiple stable output bits are required, which means unacceptable area overhead for lightweight applications. To solve this problem, configurable ROs using multiplexers and different delay units were proposed in previous papers. Unfortunately, most of them take advantage of the specific structure of a certain type of field-programmable gate arrays (FPGAs), thus not cost-saving for application-specific integrated circuit (ASIC). In this paper, we propose a configurable RO using only two hybrid logic gates in each stage for ASIC, which costs less area and power compared with previous proposals. Experiment on 50 FPGAs and one self-designed printed circuit board demonstrates satisfactory uniformity and uniqueness of this novel RO PUF. Furthermore, our proposal is proved to be reliable in a wide variety of environment conditions.