Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

• Published in: IEEE access 2024, Vol.12, p.68061-68108
• Main Authors: Srinivas, Mamidipaka B. R., Elango, Konguvel
• Format: Article
• Language: English
• Subjects: CMOS; Cryptography; Design engineering; Design for quality; Dual precharge logic (DPL); Energy consumption; fault injection attacks (FIA); Hardware; Hardware security; hardware wallets (HW); measurement-to-disclosure (MTD); Nanoscale devices; negative capacitance FET (NCFET); Physical properties; Power consumption; Resilience; Security; sense amplifier-based logic (SABL); Side-channel attacks; Silicon; Spintronics; System on chip; tamper resistance; temporal majority voting (TMV); Threat assessment; Trojan horses; Very large scale integration
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3400624

To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats. Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.