Unif-NTT: A Unified Hardware Design of Forward and Inverse NTT for PQC Algorithms

• Published in: IEEE access 2024, Vol.12, p.94793-94804
• Main Authors: Yahya Hummdi, Ali, Aljaedi, Amer, Bassfar, Zaid, Shaukat Jamal, Sajjad, Mazyad Hazzazi, Mohammad, Rehman, Mujeeb Ur
• Format: Article
• Language: English
• Subjects: accelerator; Adders; ASIC; Clocks; Computer architecture; Cryptography; Field programmable gate arrays; FPGA; hardware; Hardware acceleration; Number theoretic transform; Polynomials; post-quantum cryptography; Signal processing algorithms; Throughput
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3425813

Polynomial multiplications based on the number theoretic transform (NTT) are critical in lattice-based post-quantum cryptography algorithms. Therefore, this paper presents a platform-agnostic unified hardware accelerator design (Unif-NTT) to compute the forward and inverse operations of the NTT for the CRYSTALS-Kyber algorithm. Moreover, a unified design (Unif-BU) of the Cooley-Tukey and Gentleman-Sande butterflies is presented using two adders, multipliers, subtractors, routing multiplexers and barret-based modular reduction units. Finally, a dedicated controller is implemented for efficient control functionalities. The implementation results are realized on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The Unif-NTT requires 1664 and 1792 clock cycles for one forward and inverse NTT computations, respectively. It can operate up to a maximum frequency of 212MHz and 2.5GHz over Virtex-7 FPGA and 28nm ASIC platforms, respectively. The Unif-NTT is 26% more efficient in Area-Time-Product compared to the most area-optimized NTT accelerator from the state-of-the-art. The Unif-NTT design is suited for applications that demand reasonable hardware resources with processing speed.