Piecewise Linear Analysis of Phase-Lock Loops

The synchronizing performance of a phase-lock loop, in the absence of noise, is obtained by replacing the sinusoidal characteristic of the product demodulator, as a function of phase difference, by a triangular piecewise linear approximation. The analytical conditions for existence of a limit cycle...

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Bibliographic Details
Published in:I.R.E. transactions on space electronics and telemetry 1962, Vol.SET-8 (1), p.8-13
Main Author: Cahn, Charles R.
Format: Article
Language:English
Subjects:
Analog computers
Bandwidth
Damping
Demodulation
Frequency synchronization
Limit-cycles
Phase noise
Piecewise linear approximation
Piecewise linear techniques
Steady-state
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Summary:The synchronizing performance of a phase-lock loop, in the absence of noise, is obtained by replacing the sinusoidal characteristic of the product demodulator, as a function of phase difference, by a triangular piecewise linear approximation. The analytical conditions for existence of a limit cycle (steady-state asynchronous mode) with a steady input frequency are derived. They may be solved numerically for any limit cycle, and a constrained minimization yields the minimum mistuning of the input carrier for which a limit cycle exists. Inside of this computed synchronization limit, an asynchronous mode does not exist. The computation for a particular case (damping factor = 0.5) yields a synchronization limit very similar to previous analog computer results. It is found that for a relatively large ratio of noise bandwidth to hold-in range, the synchronization limit corresponds to a trajectory connecting adjacent unstable points in the phase plane. However, for a small ratio, the solution changes character, and the synchronization limit is found to become proportional to the square root of loop-noise bandwidth. This is in agreement with a conclusion reached by Gruen on the basis of experimental data and by Viterbi by another approximate method of analysis.
ISSN:0096-252X
DOI:10.1109/IRET-SET.1962.5008793