All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this work, we show that these signals can instead be processed in...

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Bibliographic Details
Published in:Journal of lightwave technology 2020-11, Vol.38 (21), p.5867-5874
Main Authors: Nambath, Nandakumar, Ashok, Rakesh, Manikandan, Sarath, Thaker, Nandish Bharat, Anghan, Mehul, Kamran, Rashmi, Anmadwar, Saurabh, Gupta, Shalabh
Format: Article
Language:English
Subjects:
Adaptive equalizer
Algorithms
analog coherent receiver
analog signal processing
BiCMOS integrated circuits
CMOS
Coherence
Computer networks
Data centers
Delays
Domains
Equalizers
FIR filters
Generators
High speed
Interconnections
Optical fiber communication
Optical polarization
Optical receivers
Power consumption
Signal processing
Technology assessment
Transceivers
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Summary:In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this work, we show that these signals can instead be processed in the analog domain, which can significantly reduce the power consumption and the complexity of the receiver. The first all-analog adaptive equalizer for receivers of coherent dual-polarization optical links has been presented with its detailed architecture and measurement results. The proof-of-concept equalizer uses the constant modulus algorithm for blind adaptation of its weight coefficients to implement a 4 × 4 2-tap FIR filter in 130 nm SiGe BiCMOS technology. Its functionality is evaluated experimentally for 40 Gb/s data rate and 10 km standard single mode fiber channel. This demonstration shows that the use of all-analog processing for short reach data-center interconnects is feasible and is a much simpler solution than the use of the high-speed ADC+DSP based approach. Moreover, when implemented in advanced CMOS or FinFET technologies, the power consumption of the equalizer is expected to be significantly lower than the DSP based implementations in similar process technologies.
ISSN:0733-8724
1558-2213
DOI:10.1109/JLT.2020.2987140