A 550- \mu W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental \Sigma\Delta ADC With 256 Clock Cycles in 65-nm CMOS

• Published in: IEEE journal of solid-state circuits 2019-04, Vol.54 (4), p.1161-1172
• Main Authors: Wang, Biao, Sin, Sai-Weng, U., Seng-Pan, Maloberti, Franco, Martins, Rui P.
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter (ADC); Boosting; Clocks; data weighting average; dynamic element matching (DEM); high linearity; incremental ADC (IADC); linear-exponential accumulation; Linearity; mismatch error; multi-bit; notch; sigma delta; Signal resolution; Thermal factors; Thermal noise; two phase; Very large scale integration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2888872

This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm 2 , resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.