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Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs
In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ( \alpha -IGZO n-FET) on a SiO 2 /Si (OI) substrate. The key digital fig...
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Published in: | IEEE electron device letters 2021-10, Vol.42 (10), p.1488-1491 |
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Main Authors: | , , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ( \alpha -IGZO n-FET) on a SiO 2 /Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing ( SS ) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage ( {V}_{\text {TH}} ), and SS of 91 cm 2 / \text{V}\cdot \text{s} , −0.26 V, 225 mV/decade, respectively, and those for the \alpha -IGZO n-FET are 58 cm 2 / \text{V}\cdot \text{s} , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NM H of 0.33 V, NM L of 0.22 V, and power consumption of less than 0.03 mW at {V}_{\text {DD}} of 1 V. |
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ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2021.3109343 |