A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification

Artificial intelligence workloads demand a wide range of multiply and accumulate (MAC) precision. Pitch-matching constraints in compute-in-memory (CIM) engines limit the analog-to-digital converter (ADC) precision to about 8 bits. This letter demonstrates a method of mapping a suitable input conditi...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2024, Vol.7, p.219-222
Main Authors: Vijayakumar, Balaji, Sundar, Ashwin Balagopal, Viraraghavan, Janakiraman, Bharadwaj, Varchas
Format: Article
Language:English
Subjects:
Analog to digital converters
Artificial intelligence
Compute-in-memory (CIM)
Computer architecture
Conditioning
current domain
current mirror
Current mirrors
In-memory computing
quantization
Random access memory
residue amplification
SRAM
Transistors
Vectors
Voltage measurement
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Summary:Artificial intelligence workloads demand a wide range of multiply and accumulate (MAC) precision. Pitch-matching constraints in compute-in-memory (CIM) engines limit the analog-to-digital converter (ADC) precision to about 8 bits. This letter demonstrates a method of mapping a suitable input conditioned MAC range to the input dynamic range of the on-chip 7-b ADC, thereby achieving up to 10 bits of output MAC precision. A 424 Kb SRAM CIM macro was fabricated in TSMC 28 nm, which computes 72 MACs in parallel per cycle. Measurement results at nominal supply voltage show an energy efficiency of 196.6-102 TOPS/W/b for a 2-10 bit output MAC precision. Inference results on MNIST, CIFAR10, and CIFAR100 are shown with \leq 1\% accuracy loss from the software baseline.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2024.3415476