The Design Process for Google's Training Chips: TPUv2 and TPUv3

Five years ago, few would have predicted that a software company like Google would build its own computers. Nevertheless, Google has been deploying computers for machine learning (ML) training since 2017, powering key Google services. These Tensor Processing Units (TPUs) are composed of chips, syste...

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Bibliographic Details
Published in:IEEE MICRO 2021-03, Vol.41 (2), p.56-63
Main Authors: Norrie, Thomas, Patil, Nishant, Yoon, Doe Hyun, Kurian, George, Li, Sheng, Laudon, James, Young, Cliff, Jouppi, Norman, Patterson, David
Format: Article
Language:English
Subjects:
Feeds
Hardware
Internet
Machine learning
Random access memory
Software
Software engineering
Supercomputers
Tensors
Training
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Summary:Five years ago, few would have predicted that a software company like Google would build its own computers. Nevertheless, Google has been deploying computers for machine learning (ML) training since 2017, powering key Google services. These Tensor Processing Units (TPUs) are composed of chips, systems, and software, all co-designed in-house. In this paper, we detail the circumstances that led to this outcome, the challenges and opportunities observed, the approach taken for the chips, a quick review of performance, and finally a retrospective on the results. A companion paper describes the supercomputers built from these chips, the compiler, and a detailed performance analysis [Jou20].
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2021.3058217