Optimization of device area and overall delay for CMOS VLSI designs

• Published in: Proceedings of the IEEE 1984-01, Vol.72 (6), p.670-689
• Main Author: Lewis, E.T.
• Format: Article
• Language: English
• Subjects: Analytical models; Applied sciences; Circuit simulation; Delay effects; Design automation; Design optimization; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Logic circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicides; Timing; Very large scale integration
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/PROC.1984.12916

This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.