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Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers
The design of the aerospace systems for future aircraft requires the identification of new suitable communication infrastructures that can overcome the limitations that often come with the use of the legacy, albeit well-proven, protocols that are routinely integrated into aerospace. This allows us t...
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Published in: | IEEE transactions on aerospace and electronic systems 2021-10, Vol.57 (5), p.2743-2758 |
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Main Authors: | , , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | The design of the aerospace systems for future aircraft requires the identification of new suitable communication infrastructures that can overcome the limitations that often come with the use of the legacy, albeit well-proven, protocols that are routinely integrated into aerospace. This allows us to overcome the bandwidth constraints, large deployment costs, or the lack of flexibility of other alternatives, such as SpaceWire, or legacy systems, such as the MIL-STD-1553B bus. These protocols can be replaced with new technologies that can fulfill the greater real-time and interconnectivity demands of advanced scientific probes or manned spacecraft. The advent of the new microlauncher systems has all but confirmed this trend. In this context, we describe the design and implementation of a time-sensitive networking (TSN) bus for the avionics of the Miura 1 suborbital microlauncher. TSN represents an appropriate interface for this type of platform given its ability to provide the determinism and reliability expected in space-grade systems in combination with the higher data rates (gigabit Ethernet) and greater flexibility of standard Ethernet. This has resulted in a TSN platform developed by Seven Solutions S.L. based on the commercially available Zynq-7000 devices from Xilinx. Thus, our design features a light-footprint field-programmable gate array (FPGA) architecture powered by a real-time executive for multiprocessor systems (RTEMS) operating system, which is currently pending its certification from the European space agency (ESA) for space applications. All these elements have been successfully integrated and validated for the avionics of the Miura 1 sounding rocket, which represents an illustrative case that verifies their applicability to similar scenarios. |
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ISSN: | 0018-9251 1557-9603 |
DOI: | 10.1109/TAES.2021.3061806 |