Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2012-04, Vol.31 (4), p.472-484
• Main Authors: Heloue, K. R., Onaissi, S., Najm, F. N.
• Format: Article
• Language: English
• Subjects: Complexity theory; Computational geometry; Delay; Hyperplane; Integrated circuit modeling; Logic gates; parameterized timing analysis; piece-wise planar (PWP); PVT variations; required arrival times; Runtime
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2175392

In order for the results of timing analysis to be useful, they must provide insight and guidance on how the circuit may be improved so as to fix any reported timing problems. A limitation of many recent variability-aware timing analysis techniques is that, while they report delay distributions, or verify multiple corners, they do not provide the required guidance for re-design. We propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delay at every point in the parameter space, by reporting all paths that can become critical. Using an efficient pruning algorithm, only those potentially critical paths are carried forward, while all other paths are discarded during propagation. This allows one to examine local robustness to parameters in different regions of the parameter space, not by considering differential sensitivity at a point (that would be useless in this context) but by knowledge of the paths that can become critical at nearby points in parameter space. We give a formal definition of this problem and propose a technique for solving it, which improves on the state of the art, both in terms of theoretical computational complexity and in terms of runtime on various test circuits.