On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2018-10, Vol.37 (10), p.2152-2165
• Main Authors: Burchard, Jan, Erb, Dominik, Reddy, Sudhakar M., Singh, Adit D., Becker, Bernd
• Format: Article
• Language: English
• Subjects: Automatic test pattern generation; charge-sharing; Circuit faults; circuit testing; CMOS; Defects; Delays; Fault detection; Hazards; Large scale integration; Libraries; Logic circuits; Logic gates; Pattern generation; Robustness; SAT; State of the art; Test pattern generators; transistor stuck-off; transistor stuck-open (TSOP); Transistors
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2017.2772825

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today's very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation-and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC'99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.