Power Delivery Exploration Methodology Based on Constrained Optimization

The conventional power network design process requires iterative modifications to the existing power network to eliminate hot spots and to converge to target impedance parameters. At later stages in the IC design process, this procedure may require significant time and human resources due to the lim...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2020-09, Vol.39 (9), p.1916-1924
Main Authors: Bairamkulov, Rassul, Xu, Kan, Popovich, Mikhail, Ochoa, Juan S., Srinivas, Vaishnav, Friedman, Eby G.
Format: Article
Language:English
Subjects:
Computer simulation
Cost control
Decoupling
Design methodology
Design modifications
Design optimization
Electric potential
Electric power
Electricity generation
Exploration
Global optimization
Human resources
Impedance
Integrated circuit interconnections
Integrated circuit modeling
Integrated circuits
Iterative methods
Large scale integration
Load modeling
Measurement
Optimization
Parameter estimation
power quality
power system modeling
System-on-chip
time to market
Voltage
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Summary:The conventional power network design process requires iterative modifications to the existing power network to eliminate hot spots and to converge to target impedance parameters. At later stages in the IC design process, this procedure may require significant time and human resources due to the limited flexibility to accommodate necessary changes. Power delivery exploration during early stages of the design process may bring considerable savings to the system development effort. The number of iterations may be greatly reduced by choosing the initial parameters sufficiently close to the optimum. This paper presents a power delivery exploration framework based on constrained global optimization. The power network parameters are estimated at early stages of the development process, while considering both electrical and nonelectrical factors, such as area and cost. A Laplace transform-based circuit simulator is described that is well suited for optimization purposes due to the high computational efficiency when a large number of iterations is required. The proposed framework has been applied to the distribution of voltage domains in a large scale complex integrated system, while minimizing the cost of the decoupling capacitor placement. The optimal number of voltage rails are determined, demonstrating an approximately 40% lower on-chip area than alternative solutions.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2019.2925397