Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-07, Vol.66 (7), p.2671-2684
• Main Authors: van Santen, Victor M., Amrouch, Hussam, Henkel, Jorg
• Format: Article
• Language: English
• Subjects: aging; BTI; Circuit reliability; CMOS; Defects; Degradation; Delays; Design defects; Design optimization; Electronic design automation; guardband; Integrated circuit modeling; Integrated circuit reliability; Manufacturing; Microprocessors; noise; reliability; Reliability analysis; reliability engineering; RTN; safety margin; semiconductor device reliability; Semiconductor devices; Specifications; Stability; Time dependence; Transistors; Upper bounds; Variability; variation; Variations; Work functions
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2019.2898006

Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is observable right after manufacturing, such as geometric variations, work function, and random dopant fluctuation. This is in contrast to time-dependent variability (TDV), i.e., differences in the defects of transistors, which is not macroscopically observable immediately after manufacturing. In fact, defects are electrically neutral until they capture a carrier [with mechanisms called bias temperature instability (BTI) and random telegraph noise (RTN)] and thus become observable through their induced degradation. Therefore, transistors which are characterized identically after manufacturing will drift apart during their lifetime, as their susceptibility to effects such as BTI and RTN is different. In this paper, we model for the first time TDV from a defect-centric physical perspective all the way to the circuit level. Our novel defect-centric transistor reliability specification provides a fast, yet accurate method to estimate an upper bound for TDV on the transistor level, while our novel worst cell (WCL) and worst value (WVL) libraries allow for fast evaluation of the impact of TDV on the timing of circuits. Our approach is fully compatible with existing EDA tool flows, allowing us to model and optimize complex circuits like full microprocessors. By evaluating the impact of TDV with our reliability specification and variability-aware cell libraries, we are able to model TDV, which allowed us to reduce the required defect variability guardband by 46%. In addition, we provide design optimization strategies on each abstraction level such as limiting continuous stress, transistor hardening, and implement a novel variability-aware synthesis to achieve up to 57% additional guardband reduction.