High Dynamic Range Digital Neuron Core With Time-Embedded Floating-Point Arithmetic

Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the pa...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2023-01, Vol.70 (1), p.1-12
Main Authors: Park, Jongkil, Jeong, YeonJoo, Kim, Jaewook, Lee, Suyoun, Kwak, Joon Young, Park, Jong-Keuk, Kim, Inho
Format: Article
Language:English
Subjects:
Algorithms
Arithmetic
Biological system modeling
Field programmable gate arrays
Floating point arithmetic
Floating-point synapse
Mathematical models
Membrane potentials
Memory management
Neural networks
neuromorphic processor
Neuromorphics
Neurons
Normal distribution
Parameters
Power consumption
Power management
spiking neural network
Static random access memory
Synapses
time-embedded floating-point
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Summary:Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the parameters are excessively optimized to scale up a system. This is because high-precision parameters require floating-point arithmetic - an operation known to consume high-energy and result in a high implementation cost in digital hardware. In this study, we propose a novel neuron implementation model that enhances neural and synaptic dynamics using the time-embedded floating-point arithmetic for better biological plausibility and low-power consumption. The proposed algorithm enables sharing temporal information with a membrane potential by time-embedded floating-point arithmetic, thus minimizing the memory usage of the neural state. In addition, this method need not access the static random-access memory at every time step, thus reducing the dynamic power consumption, even with a floating-point precision neural and synaptic dynamics. Using the proposed model, we implemented a core group with a total of 8,192 neurons on a field-programmable gate array device, Xilinx XC7K160T. The core group is designed for use in large-scale neuromorphic systems. We tested the neuron model in a core under various experimental conditions.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3206238