High-Speed Polynomials Multiplication HW Accelerator for CRYSTALS-Kyber

NIST has selected CRYSTALS-Kyber as the primary Key Encapsulation Mechanism (KEM) algorithm for the standardization process of post-quantum cryptography. This paper proposes a high-speed hardware accelerator targeting the polynomial multiplication of Kyber. The NTT-based algorithm is employed in Kyb...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-12, Vol.71 (12), p.6105-6113
Main Authors: Alhassani, Abdullah, Benaissa, Mohammed
Format: Article
Language:English
Subjects:
Cryptography
CRYSTALS-Kyber
Field programmable gate arrays
FPGA
hardware
Hardware acceleration
high-speed
lattice-based cryptography (LBC)
NIST
number theoretic transform (NTT)
Polynomials
post-quantum cryptography (PQC)
RNS
Table lookup
Transforms
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Summary:NIST has selected CRYSTALS-Kyber as the primary Key Encapsulation Mechanism (KEM) algorithm for the standardization process of post-quantum cryptography. This paper proposes a high-speed hardware accelerator targeting the polynomial multiplication of Kyber. The NTT-based algorithm is employed in Kyber to perform polynomial multiplication, where modular multiplication is the most time-consuming operation in the computation of the NTT. This paper proposes a new Residue Number System (RNS) methodology to perform the modular multiplication in Kyber based on fast look-up tables with a novel sub-moduli RNS decomposition of the operation into smaller tables. A high-speed polynomial multiplier FPGA accelerator is developed based on the proposed RNS modular multiplier for both single and double butterfly modes. The resulting designs were implemented on Xilinx Artix-7 FPGA, and post-place and route hardware results obtained confirmed the significant improvements over state-of-art.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2024.3427011