Fast Modulo 2^ - (2^ + 1) Addition: A New Class of Adder for RNS

Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2 n -(2 n-2 +1) addition...

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Bibliographic Details
Published in:IEEE transactions on computers 2007-04, Vol.56 (4), p.572-576
Main Authors: Patel, R.A., Benaissa, M., Boussakta, S.
Format: Article
Language:English
Subjects:
Adders
Complexity theory
Computer arithmetic
Dynamic range
Logic gates
modular adder
parallel-prefix adder
residue number system
Table lookup
Very large scale integration
VLSI
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Summary:Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2 n -(2 n-2 +1) addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130 mm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2007.1001