Geometry-Scalable Parasitic Deembedding Methodology for On-Wafer Microwave Characterization of MOSFETs

This paper presents a geometry-scalable parasitic deembedding technique for on-wafer S -parameter measurements of silicon MOSFETs. The proposed methodology is based on the transmission-line theory and the cascade and parallel combinations of two-port networks. We use only one ¿reflect¿ and one ¿thru...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2009-02, Vol.56 (2), p.299-305
Main Authors: Ming-Hsiang Cho, Chen, D., Lee, R., An-Sam Peng, Lin-Kun Wu, Chune-Sin Yeh
Format: Article
Language:English
Subjects:
Applied sciences
Deembedding
Design. Technologies. Operation analysis. Testing
Devices
Dummies
Electronics
Exact sciences and technology
Fixtures
Geometry
Integrated circuit modeling
Integrated circuits
Mathematics
Metal oxide semiconductors
Methodology
Microstrip
Microwave and submillimeter wave devices, electron transfer devices
microwave measurements
Microwave theory and techniques
Microwave transistors
modeling
MOSFETs
Networks
parasitics
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Transistors
Transmission line matrix methods
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Summary:This paper presents a geometry-scalable parasitic deembedding technique for on-wafer S -parameter measurements of silicon MOSFETs. The proposed methodology is based on the transmission-line theory and the cascade and parallel combinations of two-port networks. We use only one ¿reflect¿ and one ¿thru¿ dummy structure on a wafer to remove the feeding networks with arbitrary geometry surrounding the MOS transistors. The shielding technique is employed to improve the substrate isolation and fixture scalability. To mitigate the parasitic effects of the dangling leg between the MOSFET and the ground plane, microstriplike interconnects are introduced to mount the devices. Full-wave electromagnetic simulations were also accomplished to substantiate the interconnect scalability and network combinations. The MOS transistors and deembedding dummy patterns were implemented in a 0.13-¿m standard CMOS technology and characterized up to 30 GHz. Compared with the conventional deembedding methods, the proposed approach consumes less than 33% of chip area and characterization time for modeling test keys, while still maintaining high accuracy.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2008.2011685