50-nm Asymmetrically Recessed Metamorphic High-Electron Mobility Transistors With Reduced Source-Drain Spacing: Performance Enhancement and Tradeoffs

• Published in: IEEE transactions on electron devices 2012-01, Vol.59 (1), p.128-138
• Main Authors: Dong Xu, Xiaoping Yang, Seekell, P., Mt. Pleasant, L. M., Mohnkern, Lee, Kanin Chu, Stedman, R. G., Vera, A., Isaak, R., Schlesinger, L. L., Carnevale, R. A., Duh, K. H. G., Smith, P. M., Chao, P. C.
• Format: Article
• Language: English
• Subjects: Access resistance; Applied sciences; Electronics; Exact sciences and technology; high-electron mobility transistors (HEMTs); Logic gates; Metals; metamorphic HEMTs (MHEMTs); mHEMTs; Microwave and submillimeter wave devices, electron transfer devices; millimeter-wave transistors; MODFETs; modulation-doped field-effect transistors; Performance evaluation; Resistance; self-aligned (SAL) ohmic; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; submillimeter-wave transistors; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2172614

Whereas gate-length reduction has served as the major driving force to enhance the performance of GaAs- and InP-based high-electron mobility transistors (HEMTs) over the past three decades, the limitation of this approach begins to emerge. In this paper, we present a systematic evaluation of the impact of greatly reduced source-drain spacing on the performance of 50-nm asymmetrically recessed metamorphic HEMTs (MHEMTs). Extremely high extrinsic transconductance has been achieved over a wide drain bias range starting from as low as 0.1 V by reducing source-drain spacing to 0.5 μm with a self-aligned (SAL) ohmic process. The measured maximum extrinsic transconductance of 3 S/mm is a new record for all HEMT devices on a GaAs substrate and is equal to the best results reported for InP-based HEMTs. With the use of an asymmetric recess, SAL MHEMTs also demonstrate remarkable improvement in other major figures of merit, including off-state breakdown, on-state breakdown, subthreshold characteristics, I ON / I OFF ratio, and the voltage gain over the other SAL HEMTs reported so far. However, they still, in a few respects, under perform the conventional devices typically with 2-μm source-drain spacing. In particular, the on-state breakdown of the SAL devices has been capped at approximately 2 V, even with a very wide asymmetric recess. It appears that the uniqueness of the SAL technology would best fit applications that require low voltage and/or low DC power consumption, which can be fully tapped only when the parasitic capacitance is also properly controlled with, e.g., a high stem gate process.