Efficient Modeling of Charge Trapping at Cryogenic Temperatures-Part II: Experimental

• Published in: IEEE transactions on electron devices 2021-12, Vol.68 (12), p.6372-6378
• Main Authors: Michl, Jakob, Grill, Alexander, Waldhoer, Dominic, Goes, Wolfgang, Kaczer, Ben, Linten, Dimitri, Parvais, Bertrand, Govoreanu, Bogdan, Radu, Iuliana, Grasser, Tibor, Waltl, Michael
• Format: Article
• Language: English
• Subjects: 28-nm bulk CMOS; 4 K; advanced CMOS; bias temperature instability (BTI); CMOS; cryoelectronics; cryogenic; Cryogenic temperature; Cryogenics; Defects; Degradation; Hafnium oxide; Low temperature; MOSFETs; physical modeling; Quantum mechanics; Silicon dioxide; Stress; Stress measurement; Temperature; Thermal variables control; Threshold voltage; Trapping
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2021.3117740

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high- {k} CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO 2 and HfO 2 layer. We show that NBTI is dominated by defects in the SiO 2 layer, whereas PBTI arises mainly from defects in the HfO 2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site.