An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement

• Published in: IEEE transactions on electron devices 2022-09, Vol.69 (9), p.5074-5081
• Main Authors: Daulatabad, Shreeniwas, Swain, Peeyusha Saurabha, Gossner, Harald, Baghini, Maryam Shojaei
• Format: Article
• Language: English
• Subjects: Capacitance; CMOS; CMOS-compatible; drain-extended MOS (DeMOS); dual gate; Implants; island drain and a double-gate drain-extended MOS (IDDG DeMOS); Logic gates; MOS devices; MOSFET; MOSFETs; Performance degradation; Performance evaluation; RF device; Self alignment; Semiconductor device modeling; Semiconductor process modeling; transit frequency
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3191959

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device's RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity.