CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scali...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2023-03, Vol.70 (3), p.1-8
Main Authors: Liu, Hsiao-Hsuan, Salahuddin, Shairfe M., Chan, Boon Teik, Schuddinck, Pieter, Xiang, Yang, Hellings, Geert, Weckx, Pieter, Ryckaert, Julien, Catthoor, Francky
Format: Article
Language:English
Subjects:
Benchmark testing
Business process re-engineering
CFET
Compatibility
DTCO
Field effect transistors
Logic gates
MONOS devices
Random access memory
Routing
Scaling
Semiconductor devices
SRAM
Static random access memory
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Summary:This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2023.3235701