Yield Learning and Process Optimization on 65-nm CMOS Technology Accelerated by the Use of Short Flow Test Die

Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric/cont...

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Bibliographic Details
Published in:IEEE transactions on semiconductor manufacturing 2007-08, Vol.20 (3), p.201-207
Main Authors: DeBord, J.R.D., Sridhar, N.
Format: Article
Language:English
Subjects:
Applied sciences
Character generation
Chips
CMOS
CMOS process
CMOS technology
Contact
Contacts
Design for manufacturability (DFM)
Design. Technologies. Operation analysis. Testing
Dielectrics
Electronics
Exact sciences and technology
Failure analysis
Information analysis
Integrated circuits
Learning
Life estimation
Optimization
Production systems
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
short flow test die
System testing
Ultrasonic testing
yield optimization
yield ramp
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Description
Summary:Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric/contact loops of a 65-nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.
ISSN:0894-6507
1558-2345
DOI:10.1109/TSM.2007.901825