Optimizing FPGA Logic Block Architectures for Arithmetic

Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the computer-...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2020-06, Vol.28 (6), p.1378-1391
Main Authors: Murray, Kevin E., Luu, Jason, Walker, Matthew J. P., McCullough, Conor, Wang, Sen, Huda, Safeen, Yan, Bo, Chiasson, Charles, Kent, Kenneth B., Anderson, Jason, Rose, Jonathan, Betz, Vaughn
Format: Article
Language:English
Subjects:
Adders
Adding circuits
Arithmetic
Benchmark testing
boldsymbol Design automation
CAD
Circuit design
Computer aided design
Delay
digital arithmetic
Field programmable gate arrays
field-programmable gate arrays (FPGAs)
Hardening
logic design
Logic gates
Logic synthesis
Lookup tables
Mathematical functions
Optimization
Pins
Reduction
Table lookup
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Summary:Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the computer-aided design (CAD) flow. However, these choices have not been studied much and hence we explore a number of possibilities. We also highlight front-end elaboration optimization that helps ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains increase the performance of simple adders by a factor of 4 or more, but on larger benchmark designs that contain arithmetic improve the overall performance by 15%. Our results also show that for complete application circuits simple hardened ripple-carry adders perform as well as more complex carry-lookahead adders. Our best non-fracturable lookup table (non-fLUT) architecture with hardened arithmetic yields 12% better area-delay product than architectures without hardened arithmetic. We also investigate the impact of fLUTs and their interaction with hardened arithmetic. We find that fLUTs offer significant (12%-15%) area reduction, which is complementary to the delay reduction of hardened arithmetic. Therefore, our best fLUT architectures which use two bits of hardened arithmetic achieve 25% better area-delay product than non-fLUT architectures without hardened arithmetic.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2020.2965772