Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2020-11, Vol.28 (11), p.2424-2437
• Main Authors: Kim, Jinwoo, Murali, Gauthaman, Park, Heechun, Qin, Eric, Kwon, Hyoukjun, Chekuri, Venkata Chaitanya Krishna, Rahman, Nael Mizanur, Dasari, Nihar, Singh, Arvind, Lee, Minah, Torun, Hakki Mert, Roy, Kallol, Swaminathan, Madhavan, Mukhopadhyay, Saibal, Krishna, Tushar, Lim, Sung Kyu
• Format: Article
• Language: English
• Subjects: 25-D integrated chip (IC); and area (PPA); chiplet; Circuit design; Co-design; Computer architecture; electronic design automation (EDA) flow; Electronic systems; Instruction sets (computers); Integrated circuits; interposer; Layout; Microprocessors; power; Protocols; reliability; RISC; Routing; Silicon; System on chip; Translators; Wires
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3015494

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-onchip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs 1.29× power and 2.19× area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.