Low damage patterning of In0.53Ga0.47As film for its integration as n-channel in a fin metal oxide semiconductor field effect transistor architecture

• Published in: Journal of vacuum science & technology. A, Vacuum, surfaces, and films Vacuum, surfaces, and films, 2018-11, Vol.36 (6)
• Main Authors: Bizouerne, Maxime, Pargon, Erwine, Petit-Etienne, Camille, Labau, Sébastien, David, Sylvain, Martin, Mickael, Burtin, Pauline
• Format: Article
• Language: English
• ISSN: 0734-2101; 1520-8559
• DOI: 10.1116/1.5051505

One of the challenges of InGaAs integration as a channel in a fin field effect transistor architecture is the patterning of the III–V fin with nanometer scale definition, vertical sidewalls, and undamaged surfaces. In this work, the authors propose a two-step process to etch anisotropically and with minimal damage thin layers of InGaAs material. The first step of the process aims to modify the InGaAs surface on a well-defined thickness with limited sputtering by implanting light ions generated by a low pressure He/O2 plasma. The depth of the material modification is well controlled by the ion energy and saturates with process time, giving to this step a self-limited behavior. The second step uses aqueous HF solution to remove the modified oxidized InGaAs layer with infinite selectivity over the nonmodified InGaAs layer. The repetition of cycles of the two-step process was applied to etch the thin film of InGaAs as well as pattern using a SiN hard mask. Blanket experiments show that each cycle of the two-step process allows to remove a fixed and reproducible InGaAs thickness of 5.7 nm, while blanket SiN films are not consumed. After the process, the InGaAs surface roughness is kept intact, but the surface stoichiometry is slightly degraded with Arsenic enrichment because of the wet chemical reactions between the III-As semiconductors and the acids. The results on the pattern show that it is possible to transfer the SiN hard mask into the InGaAs layer using cycles of the two-step process with a reproducible consumed InGaAs thickness at each cycle and low sidewalls surface damage. However, the process leads to tapered InGaAs profile because of the lateral consumption of the SiN hard mask due to preferential sputtering at grazing incidence angle.