Stability Diagrams of Triple-Dot Single-Electron Device with Single Common Gate

• Published in: Japanese Journal of Applied Physics 2011-03, Vol.50 (3), p.034302-034302-9
• Main Author: Imai, Shigeru
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.50.034302

Triple-dot single-electron devices with a single common gate have been studied. The overall stability diagram of the single-electron device with a homogeneous tunnel capacitance $C_{\text{j}}$ and a homogeneous gate capacitance $C_{\text{g}}$ is derived algebraically. If the set of excess electron numbers in the three islands $(n_{1}, n_{2}, n_{3})$ is $(n, n, n)$, $(n, n + 1, n)$, or $(n, n - 1, n)$, where $n$ is an arbitrary integer, the corresponding stability region $\mathrm{S}(n_{1}, n_{2}, n_{3})$ exists for any $C_{\text{g}}/C_{\text{j}}$. $\mathrm{S}(n, n, n)$, $\mathrm{S}(n, n + 1, n)$, and $\mathrm{S}(n, n - 1, n)$ for all $n$ are arranged along the $V_{\text{g}}$ axis in the order of $n_{1} + n_{2} + n_{3}$, where $V_{\text{g}}$ is gate voltage, and neighboring stability regions overlap for any $C_{\text{g}}/C_{\text{j}}$ ratio. Overlaps between $\mathrm{S}(n, n, n)$ and $\mathrm{S}(n, n \pm 1, n)$ for all $n$ have identical kite-like shapes. Overlaps between $\mathrm{S}(n, n + 1, n)$ and $\mathrm{S}(n + 1, n, n + 1)$ for all $n$ have identical rhombus shapes. Turnstile operations are possible by alternating gate voltage around overlaps between $\mathrm{S}(n, n, n)$ and $\mathrm{S}(n, n \pm 1, n)$ and around overlaps between $\mathrm{S}(n, n + 1, n)$ and $\mathrm{S}(n + 1, n, n + 1)$, though the sequences of single-electron transfers are different. The range of drain voltage and the swing of gate voltage for turnstile operation are estimated. The overlap between $\mathrm{S}(n, n + 1, n)$ and $\mathrm{S}(n + 1, n, n + 1)$ seems superior to the overlap between $\mathrm{S}(n, n, n)$ and $\mathrm{S}(n, n \pm 1, n)$ because of the larger ratio of the drain voltage range to the gate voltage swing, though the overlap between $\mathrm{S}(n, n + 1, n)$ and $\mathrm{S}(n + 1, n, n + 1)$ might require higher reliability against the nonuniformity of gate capacitances.