Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

• Published in: Computer architecture news 2008-06, Vol.36 (3), p.203-214
• Main Authors: Wilkerson, Chris, Gao, Hongliang, Alameldeen, Alaa R., Chishti, Zeshan, Khellah, Muhammad, Lu, Shih-Lien
• Format: Article
• Language: English
• ISSN: 0163-5964
• DOI: 10.1145/1394608.1382139

One of the most effective techniques to reduce a processor’s power consumption is to reduce supply voltage. However, reducing voltage in the context of manufacturing-induced parameter variations cancause many types of memory circuits to fail. As a result, voltage scaling is limited by a minimum voltage, often called Vccmin, beyond which circuits may not operate reliably. Large memory structures (e.g., caches) typically set Vccmin for the whole processor. In this paper, we propose two architectural techniques that enable microprocessor caches (L1and L2), to operate at low voltages despite very high memory cell failure rates. The Word-disable scheme combines two consecutive cache lines, to form a single cache line where only non-failing words are used. The Bit-fix scheme uses a quarter of the ways in a cache set to store positions and fix bits for failing bits in other ways of the set. During high voltage operation, both schemes allow use of the entire cache. During low voltage operation, they sacrifice cache capacity by 50% and 25%, respectively, to reduce Vccmin below 500mV. Compared to current designs with a Vccmin of 825mV, our schemes enable a 40% voltage reduction, which reduces power by 85% and energy per instruction (EPI) by 53%