Reducing instruction fetch energy in multi-issue processors

The need to minimize power while maximizing performance has led to recent developments of powerful superscalar designs targeted at embedded and portable use. Instruction fetch is responsible for a significant fraction of microprocessor power and energy, and is therefore an attractive target for arch...

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Bibliographic Details
Published in:ACM transactions on architecture and code optimization 2013-12, Vol.10 (4), p.1-24
Main Authors: Gavin, Peter, Whalley, David, Själander, Magnus
Format: Article
Language:English
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Summary:The need to minimize power while maximizing performance has led to recent developments of powerful superscalar designs targeted at embedded and portable use. Instruction fetch is responsible for a significant fraction of microprocessor power and energy, and is therefore an attractive target for architectural power optimization. We present novel techniques that take advantage of guarantees so that the instruction translation lookaside buffer, branch target buffer, and branch prediction buffer can frequently be disabled, reducing their energy usage, while simultaneously reducing branch predictor contention. These techniques require no changes to the instruction set and can easily be integrated into most single- and multiple-issue processors.
ISSN:1544-3566
1544-3973
DOI:10.1145/2541228.2555318