What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

• Published in: Performance evaluation review 2019-01, Vol.46 (1), p.110-110
• Main Authors: Ghose, Saugata, Yaglikçi, Abdullah Giray, Gupta, Raghav, Lee, Donghyuk, Kudrolli, Kais, Liu, William X., Hassan, Hasan, Chang, Kevin K., Chatterjee, Niladrish, Agrawal, Aditya, O'Connor, Mike, Mutlu, Onur
• Format: Article
• Language: English
• ISSN: 0163-5999
• DOI: 10.1145/3292040.3219661

Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided by DRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate when compared with the real power consumed by DRAM. This is because existing DRAM power models (1) are based off of the worst-case power consumption of devices, as vendor specifications list the current consumed by the most power-hungry device sold; (2) do not capture variations in DRAM power consumption due to different data value patterns; and (3) do not account for any variation across different devices or within a device.