Characterization of Plasma Process-Induced Latent Defects in Surface and Interface Layer of Si Substrate

• Published in: ECS journal of solid state science and technology 2015-01, Vol.4 (6), p.N5077-N5083
• Main Authors: Nakakubo, Yoshinori, Eriguchi, Koji, Ono, Kouichi
• Format: Article
• Language: English
• ISSN: 2162-8769; 2162-8777
• DOI: 10.1149/2.0121506jss

Characterization of plasma-induced Si substrate damage is demonstrated using an electrical capacitance-voltage (C-V) technique customized for the nano-scale analysis. Low resistive Si wafers are exposed to an inductively coupled plasma (ICP) or a capacitively coupled plasma (CCP). We focus on the effects of plasma parameters and wet-etching processes on plasma-induced physical damage (PPD) analyses. The optical thicknesses of surface and interfacial layers (dSL and dIL) were characterized using spectroscopic ellipsometry (SE) and compared with the electrical oxide thicknesses (EOT) obtained by the C-V technique. In the case of as-damaged samples, the optical thickness dSL by SE is found to be smaller than the EOT by the C-V technique, while the sum of dSL and dIL was approximately equal to the EOT. A diluted hydrofluoric acid (DHF) wet-etch step is employed to address depth profile of defect density in damaged samples. We identify the latent defect density, dSL, and dIL after the DHF wet-etch, which are indispensible for practical device performance designs. It is found that, although the average energy of incident ions (E¯ion) is larger for the case of CCP, the latent defect density of CCP-damaged samples is smaller than that of ICP even after the wet-etching. This finding is in sharp contrast to previous pictures-the larger E¯ion leads to the thicker damaged layer and the larger latent defect density. We propose a model for these conflicting results, where the profiles of defect density and the sensitivities of each analysis technique are taken into account. The present work highlights the importance of the nano-scale damage characterization using the C-V technique, allowing to understand the influence of latent defects and to enable better design of future electronic devices.