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Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due to mechanical stress at microregion...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2014-05, Vol.53 (5S2), p.5-1-05GE04-6
Main Authors: Mizushima, Yoriko, Kim, Youngsuk, Nakamura, Tomoji, Sugie, Ryuichi, Hashimoto, Hideki, Uedono, Akira, Ohba, Takayuki
Format: Article
Language:English
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Summary:Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due to mechanical stress at microregions of the fracture surface have been studied. Such damage was evaluated by µ-Raman spectroscopy, laser microscopy, transmission electron microscopy, and positron annihilation spectroscopy. Coarse (#320 grit) grinding causes a roughly 500 MPa compressive stress, resulting in the formation of a less than 5 µm defect layer. Fine (#2000 grit) grinding enables the formation of a plane surface and reduces the stress to 100-200 MPa. However, a damaged layer of 200 nm still remains and an almost 100-nm-thick layer of vacancy-type defects exists. After chemical mechanical polishing (CMP), a stress-free surface was obtained and no defects were found except atomic-level vacancies, which were detected in a layer of 4 nm thickness after 1 µm CMP.
ISSN:0021-4922
1347-4065
DOI:10.7567/JJAP.53.05GE04