Design of Linear Systolic Arrays for Matrix Multiplication

This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to...

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Bibliographic Details
Published in:Advances in electrical and computer engineering 2014-02, Vol.14 (1), p.37-42
Main Authors: MILOVANOVIC, E. I., STOJCEV, M. K., MILOVANOVIC, I. Z., NIKOLIC, T. R.
Format: Article
Language:English
Subjects:
Accelerators
address generator units
Architecture (computers)
Criteria
Gain
Hardware
linear systolic arrays
Mathematical models
matrix multiplication
Multiplication
Systolic arrays
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Summary:This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.
ISSN:1582-7445
1844-7600
DOI:10.4316/AECE.2014.01006