HSP-V: Hypervisor-Less Static Partitioning for RISC-V COTS Platforms

Virtualization technology has played a pivotal role in consolidating Mixed-Criticality Systems (MCS) onto a single computing platform. However, not all RISC-V processors present in Commercial Off-The-Shelf (COTS) platforms feature the so called Hypervisor extension, which poses a significant challen...

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Bibliographic Details
Published in:IEEE access 2024-01, Vol.12, p.71131-71144
Main Authors: Sousa, Joao, Martins, Jose, Gomes, Tiago, Pinto, Sandro
Format: Article
Language:English
Subjects:
Eletrónica e Informática
Engenharia e Tecnologia
Engenharia Eletrotécnica
Field programmable gate arrays
Hardware
Indústria
inovação e infraestruturas
Interference
Mixed-criticality systems
OpenSBI
Partitioning
Platforms
Protection
Reduced instruction set computing
RISC
RISC-V
Software
static-partitioning
Virtual machine monitors
Virtualization
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Summary:Virtualization technology has played a pivotal role in consolidating Mixed-Criticality Systems (MCS) onto a single computing platform. However, not all RISC-V processors present in Commercial Off-The-Shelf (COTS) platforms feature the so called Hypervisor extension, which poses a significant challenge in offering hardware virtualization capabilities in existing RISC-V silicon. This paper introduces HSP-V, a ready-to-run low-level software stack to provide static partitioning on RISC-V COTS platforms lacking hardware virtualization support. HSP-V leverages the Domain feature of the RISC-V Open Source Supervisor Binary Interface (OpenSBI) reference implementation to define partitions protected by the Physical Memory Protection (PMP) unit. Additionally, it provides other capabilities such as interrupt partitioning, direct interrupt injection, cache partitioning, and platform-level isolation for DMA-capable devices. The conducted evaluation assesses the impact of HSP-V on different empirical metrics, including domain boot time, interrupt latency, code size, and execution performance using micro and application benchmarks (LMBench and MiBench, respectively). HSP-V achieves highly deterministic interrupt latency with an average execution time of 457 ns (with a standard deviation of only 22 ns), with essentially zero traps in the Domain execution. In scenarios with cache interference, the HSP-V keeps the performance overhead as low as 0.39% for the best case scenario. Finally, all work described in this article is publicly available and open-sourced for the community to further evolve, port, and evaluate HSP-V in other hardware platforms.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2024.3399601