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Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full‐Adder Functions with Memristor Crossbar for Beyond von Neumann In‐Memory Computing

The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a res...

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Bibliographic Details
Published in:Advanced science 2022-05, Vol.9 (15), p.e2200036-n/a
Main Authors: Song, Yujie, Wang, Xingsheng, Wu, Qiwen, Yang, Fan, Wang, Chengxu, Wang, Meiqing, Miao, Xiangshui
Format: Article
Language:English
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Summary:The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a resistor, arbitrary Boolean logic can be reconfigured and calculated in two steps, while no additional voltage sources are needed beyond “±VP” and 0, and all state reversals are based on memristor set switching. Utilizing the proposed logic scheme in an elegant form of unity structure and minimum cost, the implementation of a 1‐bit adder is demonstrated economically, and a promising circuit scheme for the N‐bit adder is exhibited. Some critical issues including the crosstalk problem, energy consumption, and peripheral circuits are further simulated and discussed. Compared with existing works on memristive logic, such methods support building a memristor‐based digital in‐memory calculation system with high functional reconfigurability, simple voltage sources, and low power and area consumption. This study proposes and successfully verifies by experiments the 16 Boolean logics with a reconfigurable and uniform logic circuit consisted of two memristors and one resistor, implemented in two steps, demonstrating the advantages in speed, power, area, and implementation efficiency. 1‐bit full adder is demonstrated and N‐bit full adder scheme is proposed and discussed.
ISSN:2198-3844
2198-3844
DOI:10.1002/advs.202200036